(Second from left) Jay Y. Lee, Government chairman of Samsung Electronics, poses for a photograph throughout his go to to ZEISS headquarters on April 26, 2024. [Photo provided by Samsung Electronics Co.]
Jay Y. Lee, government chairman of Samsung Electronics Co., visited the headquarters of worldwide optics firm ZEISS Group in Germany to debate potential partnerships.
Lee visited the ZEISS headquarters in Oberkochen, Germany, on Friday, and mentioned cooperation within the discipline of nanometer processes, the corporate stated on Sunday.
ZEISS is the unique provider of optical techniques to ASML Holding N.V., the Dutch producer of utmost ultraviolet (EUV) lithography techniques.
“Collaboration with ZEISS will allow us to enhance the efficiency and manufacturing processes of next-generation semiconductors and improve yield,” Samsung Electronics stated.
The corporate added that it goals to guide the sub-3-nanometer ultra-fine course of within the foundry market and begin mass manufacturing of Sixth-generation, 10-nanometer DRAMs utilizing EUV processes by the top of the yr.
Lee‘s go to to Germany follows the latest announcement by competitor Taiwan Semiconductor Manufacturing Co. (TSMC) of its 1.6-nanometer course of roadmap.
TSMC, which beforehand deliberate a 2-nanometer course of by 2025 and a 1.4-nanometer course of by 2027, has set off a race with its 1.6-nanometer course of roadmap.
Samsung Electronics, nonetheless, is assured that its Gate-All-Round (GAA) expertise will make it the market chief within the 2-nanometer course of.
Initially developed by Samsung Electronics, GAA expertise provides superior energy effectivity and efficiency in comparison with standard fin-shaped field-effect transistor (FinFET) constructions.
The chipmaker efficiently mass-produced 3-nanometer chips utilizing GAA expertise in 2022 for the primary time on the earth.
[Photo provided by Samsung Electronics Co.]
Samsung Electronics is the one firm to make use of GAA expertise in its foundry course of, whereas TSMC has plans to start the use from the 2-nanometer course of, though it faces decrease yields than TSMC.
Lee has mentioned yield enchancment measures with ZEISS executives.
“Increasing cooperation on EUV expertise and superior tools will enhance yield,” the corporate stated, including that the pilot utility of digital twin expertise utilizing synthetic intelligence and large information in chip manufacturing will start subsequent yr.
With the growing complexity of high quality processes, the significance of packaging has been rising.
Samsung Electronics has been accelerating the event and commercialization of X-Dice, a 3D packaging expertise, and constructing the 20 trillion gained ($14.5 billion) next-generation semiconductor analysis and growth (R&D) complicated at its Giheung services.
Lee has additionally been energetic in holding talks with world expertise CEOs about AI chip cooperation.
In February, he met with Meta Platforms Inc.’s Mark Zuckerberg in Seoul, and early final yr he held conferences with ASML‘s Peter Wennink and Nvidia Corp.’s Jensen Huang.
In 2019, Lee declared the “System Semiconductor Imaginative and prescient 2030,” beneath which the corporate goals to guide the system chip market by growing funding to 171 trillion gained from 133 trillion gained.
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